The invention relates generally to video graphics processing and more particularly to a method and apparatus for compressed texture caching in a video graphics system.
Computers are used in many applications. As computing systems continue to evolve, the graphical display requirements of the systems become more demanding. This is especially true in applications where detailed three-dimensional graphical displays must be updated quickly. One example of such an application is a computer game where movement and modification of background images may place great demands on the processing power of the computing system.
In order to display some screen images, detailed textures are stored in memory. These textures are digitized images drawn onto three-dimensional shapes to add visual detail. One example is a brick pattern that would be mapped onto a wall structure, and if the walls extending into the distance, the texture will be mapped in such a way as to show perspective.
The use of detailed textures can consume a large amount of available memory bandwidth in a video graphics systems as the textures may need to repeatedly be read from memory for use in texturing operations. As texture mapping operations consume more and more of the available memory bandwidth in video graphics processing circuits, overall performance of these video graphics circuits may be compromised. This is due to the fact that other circuit blocks also require access to the memory that stores the textures. If the texturing operations monopolize use of the memory, these other circuit blocks may be unable to properly perform their functions in a timely manner and, as a result, may degrade the performance of the video graphics system as a whole.
One prior art solution that reduces memory bandwidth associated with reading texture data stores portions of the textures in a cache included in the video graphics circuit. Recently used texture data that is still in the cache does not have to be retrieved from memory each time it is reused. However, in order to be effective, the cache must be of a relatively large size. Large caches consume a large amount of die area in integrated circuit solutions, and therefore add to the cost of video graphics systems that utilize such large caches.
Another prior art solution utilizes compression techniques to compress the texture data in the memory structure. When texture data is required from memory, it is decompressed prior to use. However, in these systems data that is reused repeatedly must be fetched and decompressed from memory each time it is used. Although memory bandwidth is reduced by the reduction in the amount of data that must be repeatedly retrieved from memory, the bandwidth required to retrieve the compressed data and decompress it is still substantial.
Another hybrid prior art solution employs both compression and caching in a technique that stores compressed texture data in memory and decompresses the texture data as it is retrieved for use in texturing operations. After the texture data is decompressed, it is stored in an on-chip cache such that repeated use of the same texture data would be possible without additional memory bandwidth of the external texture memory being utilized. However, this solution still suffers from the additional cost associated with a large cache structure.
Therefore, a need exists for a method and apparatus that reduces memory bandwidth usage for texturing operations while limiting the size of any cache structures used to store texture data.